1. Field of the Invention
The present invention generally relates to a method for forming an embedded non-volatile memory, and more particularly to a method for forming a plurality of separated spacer width in an embedded non-volatile memory to prevent leakage current.
2. Description of the Prior Art
Typical semiconductor memory utilized during microprocessor operation is volatile. That is in the case of power interruption, the data stored in the semiconductor memory is typically completely lost. One way to circumvent this problem is to provide separate backup of the memory, such as battery power or capacitor storage. An alternate technique is to make the memory fundamentally non-volatile. This option is highly desirable because non-volatile semiconductor memories would not only withstand, power interruption, but also would be stored or shipped without being energized.
Non-volatile memory devices are important for providing an advantage that random access memory (RAM), both dynamic and static, can""t be provided. That is, non-volatile memory devices do not lose their memory even the power is turned off. RAM enables information to be both stored and read to a memory cell as dictated by a microprocessor. Read-only memory (ROM) is the most popular variety of non-volatile memory devices.
However, the flash memory is electrically re-programmable for a limited number of times. This makes it ideal for those applications where only a few changes in the programming of the system is for either the entire memory array or for blocks of it.
Besides, memory storage exists not only as stand-alone memory device, but also embedded in processor chips. The performance of an embedded flash can be better than other flash since bandwidth problems are reduced and interface circuit and package leads are eliminated. It can also have characteristic tailored to the specific application rather than being a standardized comprises between many factors such as high operating speed.
Referring to FIG. 1A, the substrate 100 is divided into at least two a memory array 100a and a logic device area 100b. The conventional method for forming the first dielectric layer (tunneling oxide layer) 102a on the substrate 100 by thermal oxidation. However, the dielectric constant value of first 102a and second dielectric layer 102c is about 3.8 to 3.9 and thermal oxidation is a high temperature process. Then, a charge storage layer 102b such as silicon nitride (SiN) formed on the first dielectric layer 102a by conventional CVD method (chemical vapor deposition method). Next, a second dielectric layer 102c formed on the charge storage layer 102b by conventional CVD method. The material of first 102a and second dielectric layer 120c is silicon oxide. According to the hot electron injection phenomenon (HEI), some hot electrons penetrate through the bottom first dielectric layer 102a, especially when first dielectric layer 102a is thin enough, and electrons are therefore collected in charge storage layer 102b. 
Referring to FIG. 1B and FIG. 1C, a photoresist layer is formed on the second dielectric layer 102c. Then, an etching process is to remove the second dielectric layer 102c, charge storage layer 102b, and first dielectric layer 102a on logic device area 100b. Then, a gate oxide layer 104 is formed on the logic device area 100b, after the photoresist layer is removed, and a polysilicon layer 106 is deposited on the memory array 100a and logic device area 100b. Next, a word line is defined on memory array 100a and another photoresist layer is formed on the polysilicon layer 106. Then, an etching process is performed on polysilicon layer 106 to form poly gate electrodes 106 on the memory array 100a and logic device area 100b simultaneously.
Referring to FIG. 1D, a silicon oxide is deposited to fill the pitch between the poly gate electrodes 106. Then, an etching back process is performed on the silicon oxide to form spacers 110 on sidewall of the poly gate electrodes 106. Then, a self-aligned silicide process is formed over the poly gate electrode 106.
Referring to FIG. 1E is a vertical view of the memory device. The horizontal lines connected to all the cells in the row are called word lines 112a, 112b, 112c, and 112d, and the vertical lines (along which data flows into and out of the cells are called bit lines 114a, 114b, 114c, and 114d. The dotted line 116 is crosscut the word line 112a, 112b, 112c, and 112d. Due to the thickness of oxide/nitride/oxide layer 102 is thinned; the salicide will pass through the oxide/nitride/oxide layer 102 to the substrate 100 in self-aligned salicide process such that the semiconductor device will not be operated.
The most obvious limiting factor for an embedded flash memory is the relevant fabrication. In conventional fabrication, the transistors of memory array and logic device area are formed simultaneously; therefore, the quality of transistors of both memory array and logic device area can""t be optimized at the same time. In other words, either performance of any transistors of logic device area is degraded or reliability of any memory array is degraded.
It is an object of this invention to provide separated spacer width to create an effective oxide thickness that can avoid a conduction film formed from self-aligned silicide process between bit line to bit line.
It is another object of this invention to prevent the leakage path is between bit line to bit line in self-aligned silicide process.
It is still another object of this invention to provide a separated adjust photo condition of memory array and logic device area to get optimum process windows.
It is still another object of this invention to improve the photo condition process windows of the word line and complementary metal-oxide semiconductor (CMOS) poly gate electrode to prevent the leakage between the bit line to bit line.
In one embodiment, a substrate has a bit line structure and a plurality of isolation devices. The substrate is divided at least a memory array and a logic device area. The transistors of memory array are formed firstly and the pitch width between poly gate electrodes is equivalent in memory array. And then, the transistors of logic device area are formed and the pitch width between the poly gate electrodes is not equivalent in logic device area. By using separated adjust photo condition of memory array and logic device area to get optimum process window and using separated spacer width in memory array and logic device area to avoid the leakage path in self-aligned salicide process.